Microsemi Corporation became the first programmable logic device (FPGA) supplier to provide a comprehensive software tool chain and intellectual property (IP) core for RISC-V design. Its RV32IM RISC-V core is suitable for Microsemi IGLOO2 FPGA, SmartFusion2 System-on-Chip (SoC) FPGA or RTG4 FPGA, with Eclipse-based SoftConsole integrated development environment (IDE) and Libero SoC design suite running on Linux platform, providing comprehensive Design support.
The new RV32IM RISC-V core developed by Microsemi and SiFive enables customers to use the Open Instruction Set Architecture (ISA) for design, through a licensed BSD authorization, to achieve full portability and a more secure processor architecture. RISC-V is a new ISA, and now it is a standard open architecture regulated by RISC-V FoundaTIon. RISC-V provides compelling software processor solutions for Microsemi's low-power, reliable, and secure FPGAs. The RV32IM RISC-V core opens the door to a new generation of innovation for embedded designers. Now, engineers can rely on an open ISA, do not need to be constrained by a single supplier, and can use open source tools and hardware. Never before has any processor allowed designers to check, modify, rewrite, collaborate on their designs, and migrate their designs to the best platform most suitable for their products. Microsemi's low-power FPGAs with security, embedded flash memory are ideal for this new paradigm.
Venki Narayanan, Senior Director of Software and Systems Engineering, Microsemi SoC Products Group, said: "Our IGLOO2, SmartFusion2 and RTG4 devices are ideal FPGAs for building RISC-V cores. We reduce power consumption by up to 50% and provide customer IP with experience Proven security. RISC-V is very suitable for restarting the construction of processor capabilities for security, trust and reliability, which are the core of Microsemi’s solution. We will further invest in this architecture, Ensure that customers have the support of a long-term roadmap, thereby continuing to consolidate our leading position in this technology field."
Now, customers seeking to develop custom devices can integrate their designs into Microsemi’s FPGAs, allowing their solutions to be introduced to the market faster. The combination of Microsemi's IGLOO2 FPGA, SmartFusion2 SoC FPGA or RTG4 FPGA and its Libero SoC design kit creates an ideal platform for RISC-V cores for a variety of embedded applications, and its size and power consumption make it very easy to implement. Microsemi's safe low-power FPGA series provides customers with an effective architecture that allows them to protect their IP and ensure that their designs can be supported in the industrial, defense, security and medical markets for long-term. The Libero SoC design suite allows designers to implement their designs and efficiently utilize FPGA logic elements (LE) to obtain cost-effective solutions. The Eclipse-based SoftConsole IDE runs on Linux, enabling users to compile and debug their source code. This IP core and software platform is the first comprehensive RISC-V solution for FPGA.
Since register transfer level (RTL) source code is available for inspection, this new RV32IM RISC-V core is very suitable for applications such as safety and security. For example, customers can verify the safety of the processor themselves, which is impossible with other closed architecture processors. In safety-critical applications, customers can run several RISC-V cores, and when one of them fails, ensure that there is a redundant core to take over.
Rick O'Connor, Executive Director of RISC-V FoundaTIon said: "We are very pleased that Microsemi has released RISC-V intellectual property cores for its IGLOO2, SmartFusion2 and RTG4 FPGAs. The company's comprehensive Linux-based tool chain will enable a wide range of customers Develop RISC-V cores in Microsemi’s FPGA devices. I highly praise Microsemi’s leadership in launching this comprehensive RISC-V platform. Our foundation looks forward to working with them to explore future developments."
Microsemi participated in the creation of RISC-V FoundaTIon in the early stage, thereby establishing a leadership position in the new standard and ecosystem. It is currently and is working closely with non-profit organizations to ensure that ISA becomes an industry standard for a wide range of computing devices. Ted Speers, head of product architecture and planning for Microsemi's SoC business unit, was appointed as the first board member of RISC-V FoundaTIon in July 2016, and Ted Marena, SoC FPGA marketing director, was recently elected as the vice chairman of the RISC-V marketing committee .
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