Based on the 0.18μm 1P3M 45V BCD process design, an asynchronous BUCK DC-DC chip for electric meter system is implemented. The application environment of BUCK DC-DC in the electric meter application system is introduced, the control loop structure of CCM current mode PWM modulation mode is designed, the compromise of DC-DC system parameters is analyzed, and the Matlab tool modeling is used to verify. The ESD protection scheme is designed and the packaging scheme is given. After the tape-out verification, the test results show that the functions and performance indicators of the chip meet the design requirements.
1 Introduction
The smart meter system is composed of metering, MCU, display and drive, storage, communication (including modules), power management, etc. It is necessary to consider the power supply solution of each chip of the entire system.
The PLC carrier module is powered by a single power supply, the working voltage is 3.3 V / 5 V/12 V, and the power consumption during communication
The BUCK DC-DC chip in this article is a 45 V 600 mA BUCK DC-DC converter IC specially optimized for the market demand of electric meters. The circuit has a wide input voltage range (4.5 V~45 V), high efficiency, low output ripple (less than one thousandth), low temperature coefficient (less than five thousandths of the full temperature range), and the maximum typical output current is 600 mA.
The circuit uses a current-mode feedback loop architecture to provide fast loop response. The circuit uses a 1.6 MHz fixed frequency PWM modulation method. It can support extremely small external components, including input and output ceramic capacitors and inductors. Chip SOT23-6 package.
At present, the BUCK DC-DC in the electric meter system is matched with a transformer coil to take electricity from the AC power supply. It is in the position of a step-down DC-DC regulator. It requires a wide range of input voltage and also requires a production process. Higher. The load of this DC-DC is mainly PLC carrier module, etc., which has a very large application market.
The BUCK DC-DC chip is designed and implemented based on 0.18 μm 1P3M 45V BCD process technology, and its technical level reaches and exceeds that of similar products at home and abroad. The application of high-voltage DC-DC technology is very extensive, mainly for high-end markets such as automobiles, industrial control, and power meters. This circuit design is mainly aimed at domestic and some overseas electric meter markets.
2 System application environment
Figure 1 shows the system application diagram when the output voltage is 12 V. The front stage is the output of the transformer that takes power from the AC grid, and the back stage is the PLC carrier module. An external freewheeling diode (asynchronous rectification) is required, and the inductance value can be set between 2.2 μH and 47 μH according to the system design scheme. The feedback capacitance of 33 pF determines the position of a zero point, which can be selected according to the needs of system loop stability. The input and output nodes are respectively added with voltage-stabilizing filter capacitors to obtain better input and output ripple characteristics.
3 Internal system design
Figure 2 shows the system design block diagram of the BUCK DC-DC chip. This chip adapts to a wide input power range, 4.5 V to 45 V, built-in upper switching tube (NMOS), uses asynchronous rectification, uses an external Schottky diode for freewheeling, and a wide inductance range (2.2 μH ~ 47 μH).
Built-in compensation circuit, built-in soft start circuit. Built-in current peak detection circuit, short circuit protection short circuit, over temperature protection circuit. Fixed working frequency PWM modulation mode, current mode.
The system structure of the synchronous step-down power converter based on the bootstrap scheme adopts a common source level structure to achieve strong driving capability to power VBST, avoiding direct comparison with the analog power supply (VDD), thereby reducing frequent switching of the bootstrap circuit Interference to the analog power supply in the process. It can support applications with large duty cycle and large load current.
Adopting a cleverly realized design of the power switch current detection circuit structure, so that the final output current sampling detection gain is only related to the ratio of the size of the MOS tube and the ratio of the two resistor strings, eliminating the process, temperature, and power supply voltage The impact of the PVT is not affected by the accurate output current sampling detection. Even if the process fluctuates greatly and the temperature fluctuates greatly, the current can be accurately detected. The slope compensation current is realized by accumulating the sampling current of the power switch current and the slope compensation current into a voltage value and then feeding it back to the PWM voltage comparator, thereby completing the current feedback loop of the power converter. On the basis of this structure, the realization circuit of current peak detection is realized very simply.
A PWM waveform generation circuit on the current loop is designed, which can optimize the output ripple when working with a large duty cycle. The output ripple amplitude can achieve within one thousandth of the output voltage.
4 The balance of DC-DC system indicators
One of the difficulties in the design of this chip is the balance of the DC-DC system indicators, especially how to balance the system indicators when the external conditions such as Vin/Vo/L/Co/Io vary widely.
Regardless of whether the current mode or the voltage mode is used in the feedback loop of the PWM modulation method, a slope compensation voltage is required. Can the output duty cycle automatically return to the ideal value when there is a slight fluctuation in the output? If slope compensation is not added, when the theoretical duty cycle is greater than 0.5, the output current will tend to diverge and oscillate if there is a slight disturbance in the output current.
Assuming that ml and m2 are the rising and falling rates of the output current, respectively, if the slope compensation slope is -ma after the compensation slope is added. It can be proved that the slope of slope compensation needs to satisfy ma> 0.5×m2 = 0.5×Vo/L, so that the system can be stable [2]. In order to obtain a sufficient slope compensation slope value, the compensation current must be set according to the slope of the inductor current drop. The problem is that the slope m2 of the output current drop is directly proportional to the output voltage. Therefore, the ramp current is preferably proportional to the output voltage. If the slope compensation current is fixed, the compensation current must be determined according to the maximum output voltage (because when the output voltage is the maximum, m2 is the maximum and m1 is the minimum). Generally speaking, the value is around ma = 0.7×m2. However, over-compensation also has risks, reducing system dynamic performance and reducing maximum peak current capability (thus limiting the final output drive capability).
When the system is working in the CCM state, it must meet the minimum compensation slope required for stability. If ma = 0.5×m2 = 0.5×Vo/L,
If ma = n×m2 = n×Vo/L,
Then the maximum value equivalent to the current peak value Ipeak at EAOUT is
Discussion (1) When n> 0.5, Ipeak_max decreases with increasing Vin. In the case of normal current output, Io
(2) n
Assuming that the application needs to select the typical value of the output current from 0 to 660 mA, that is, when the system is required to work at a large duty cycle (maximum compensation), it can still output 660 mA.
Based on the above Ipeak_max formula for discussion, analyze the maximum value of Ipeak_max when Iomax = 660 mA, fsw = 1.6 MHz (Ts = 0.625 μs), Vo = 12 V and the compensation slope is 0.7×Vo/L (ie n = 0.7). variation range. Figure 3 shows the result calculated by Matlab, where the variables are only Vo, Vin, and L.
From the results, the change of Vin has little effect on Ipeak_max. The influence of Vo and L is much more obvious. This Ipeak_max is the limit of the current range corresponding to the EA output voltage range, that is, the current range corresponding to the EA output voltage range is required to be larger than the range in all cases. From the results of Matlab calculations, it is impossible if all inclusions are greater than 5 A. Therefore, the EA output range can only be as large as possible, but it cannot take into account all applications. Sometimes L is very small, the duty cycle is very large, or both cannot meet the requirements.
For example, if you set Gcs=1 A/V and EAOUTmax = 3.1 V, the Ipeak_max that EAOUT can support = EAOUTmax×Gcs = 3.1 A. If Gcs = 0.66 A/V and EAOUTmax = 3.1 V are set, the Ipeak_max that EAOUT can support = EAOUTmax×Gcs = 2.046 A. Therefore, increasing Gcs or increasing the upper limit of EAOUT can increase the Ipeak_max supported by EAOUT.
Based on Ipeak_max = EAOUTmax×Gcs = 3.1 A, when Vo = 12 V, fsw = 1 MHz, and Iomax = 660 mA, according to the value of Vin, the minimum usable inductance value L is obtained as shown in Table 1 The minimum L determined by Vin, Figure 4 Optimal solution of Power MOS SIZE and drive circuit.
In addition, Matlab can also be used to model the power loss to obtain the optimal solution of Power MOS SIZE and drive circuit [3]. The rising edge is set to 25 ns and the falling edge is set to 6 ns. Use the Matlab model to scan the Power MOS SIZE, and the results are shown below. fsw = 1.6 MHZ, L = 47μH, priority is given to the application of Vin = 14 V, Vo = 12 V, Io = 120 mA. When Ron = 0.413 Ω, it is the optimal solution.
5 ESD solution design and implementation
The working range of the pins of this BUCK DC-DC circuit is more complicated, Vin = EN = (-0.3 V~ 45 V), FB = (-0.3 V~ 6 V), LX = (-0.3 V ~ Vin +0.3 V ), BST-GND = LX + 6 V, BST-LX = (-0.3 V ~ 6 V), HBM 2 kV ESD test is required in typical applications. The ESD implementation scheme adopted is shown in Figure 5.
Since this chip is a power supply design scheme, the power supply scheme between the PIN pins is complicated, so we choose to adopt a common ground path method, that is, all ESD paths form paths through a common ground ring. SCR IP is used between the high voltage pin and GND to save area, the GGN MOS structure is used between the low voltage pin and GND, and the low voltage GGN MOS structure with NBL and deep well isolation is used between BST and LX, and the input port is added Secondary protection structure.
5 verification
All circuit simulation tests are based on 0.18μm 1P3M 45 V BCD process. The power supply voltage Vin is in the range of 4.5 V to 45 V, and the temperature is in the range of -40 ℃ to 85 ℃. Use Cadence's SPECTRE to perform module and full chip simulation verification on the circuit. The die and package seen after DECAP of this BUCK DC-DC mass-produced chip are shown in Figure 6, which is packaged in SOT23-6.
Through tape-out verification, the chip's functions and performance indicators meet the defined requirements, and the no-load standby quiescent current is only about 600 μA. Input 16 V, output 12 V, L = 47μH, load current 300 mA, the efficiency is as high as 95.6%.
The effect of different load current and input voltage on efficiency is shown in Figure 7. The influence of different load currents on the output voltage is shown in Figure 8. The influence of different input voltages on the output voltage is shown in Figure 9. Figure 10 shows the output ripple test result (Vin = 18±1 V, 220 V transformer power supply, Vo = 12 V, Io = 120 mA, output capacitance 10μF + 0.1μF + 470μF, inductance 47 μH, input capacitance 2200 μF, Oscilloscope bandwidth 20 MHz). In the full temperature range of -40°C to 85°C, the change in output voltage can be controlled within five thousandths of the output voltage. A small input and output voltage difference can be achieved. When Vout = 12 V and a load current of 600 mA are fully loaded, the minimum voltage difference can be as low as 0.72 V. In accordance with the standard MIL-STD-883H Method 3015.8 test in Shanghai Yishuo, it passed the 2 kV HBM ESD test. The products are currently sold in the market.
4 Conclusion
This article has implemented an asynchronous BUCK DC-DC chip based on the 0.18μm 1P3M 45 V BCD process design. The application environment of BUCK DC-DC in the electric meter application system is introduced, the control loop structure of the current mode PWM modulation mode of CCM is designed, the compromise of DC-DC system parameters is analyzed, and the Matlab tool modeling is used for verification. The ESD protection scheme is designed and the packaging scheme is given. After the tape-out verification, the test results show that the functions and performance indicators of the chip meet the design requirements.
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