The EPP protocol is compatible with the standard parallel port protocol and can complete the bidirectional transmission of data. It provides four data transmission cycles: data write cycle; data read cycle; address write cycle; address read cycle. Although the use of domain names is the original motivation of EPP, the goal of the protocol design is to apply to any order and execution system. The EPP protocol is based on the XML (structured text) format, and the underlying network transmission is not fixed. Although the only method currently specified by the EPP bubble is through TCP, the flexible design of the protocol also allows its use such as BEEP, SMTP, SOAP Or other means of transmission. The agreement was finalized by the IETF's provreg working group in 2004. In August 2009, the IETF recognized the full standard status of EPP.
In the design, we use the data cycle for data transmission between the laptop and the acquisition board, and the address cycle for address transmission and gating. Table 1 lists the pin definitions of the DB25 socket in the EPP protocol.
Table 1 EPP signal definition
| EPP signal | direction | DB25 corresponding feet | description |
| nWrite | out | 1 | Low level write, high level read |
| nDataSTB | out | 14 | Low effective, data read and write |
| nAddrSTB | out | 17 | Low effective, address read and write |
| AD [8: 1] | Bi | 2 ～ 9 | Bidirectional data / address line |
| GND | 18 ～ 25 | Ground | |
| nReset | out | 16 | Active low, peripheral reset |
| NINTR | in | 10 | Peripheral interrupt, generated to the host |
| An interrupt request | |||
| nWait | in | 11 | Handshake signal, low means you can start a |
| Read and write cycle, high means OK | |||
| End a read and write cycle | |||
| Userdfn | in | 12/13/15 | Flexible definition according to different peripherals |
(1) The program performs an I / O write cycle and writes data to Port 4 (EPP data register).
(2) nWrite goes low and the data is sent to the serial port.
(3) Since nWait is low, it indicates that a data write cycle can be started, and nDataSTB becomes low.
(4) Wait for the handshake signal of the peripheral (wait for nWait to go high).
(5) nDataSTB goes high and the EPP cycle ends.
(6) The ISA I / O cycle ends.
(7) nWait goes low, indicating that the next data write cycle can begin.
It can be seen that the entire data transfer process takes place within an ISA I / O cycle, so using the EPP protocol to transfer data, the system can obtain a transmission rate close to the ISA bus (500k ~ 2M byte / s).
Easy Electronic Technology Co.,Ltd , https://www.nbpcelectronicgroup.com