D Trigger: When the master-slave trigger triggered by a negative edge is active, the input signal must be added before the positive edge. If an interfering signal is present at the input during CP high, it is possible to make the state of the flip-flop error. The edge trigger allows the input signal to be added just before the CP trigger edge comes. In this way, the time at which the input is disturbed is greatly reduced, and the possibility of interference is reduced. Edge D flip-flops are also referred to as sustain-block edge D flip-flops.
Circuit structure: The flip-flop consists of six NAND gates, where G1 and G2 form the basic RS flip-flop.
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