Abstract: This paper designs and implements the signal modulation system of digital audio broadcasting system in FPGA chip. The signal modulation system is located at the end of the baseband signal processing chain of the entire digital audio broadcasting system and is the core system of baseband digital signal processing. According to the Eureka 147 standard, the signal modulation system requires a series of processing such as digital modulation, frequency domain interleaving, differential modulation, and orthogonal frequency division multiplexing on the input baseband code stream. The designed signal modulation system can process the input baseband code stream in real time, complete the above signal processing algorithm, and output the baseband signal of the digital audio broadcast.

introduction

Digital Audio Broadcasting (DAB) is the product of the evolution of analog communication to digital broadcasting systems. Among the many digital audio system solutions, the Eureka 147 DAB system is the earliest and the most developed digital audio system. The DAB baseband signal modulation system designed in this paper is based on the technical requirements of the Eureka 147 system.

In this paper, based on the model-based system design method, the algorithm layer of each module of DAB baseband signal modulation system is firstly modeled. Then, the algorithm layer model of the system is converted into programmable using the Simulink platform and the programmable hardware model library provided by Xilinx. The hardware model, finally using Xilinx's System Generator software to automatically convert the proven Simulink model into an FPGA for engineering.

1 Introduction to DAB Signal Modulation System

The DAB system baseband signal processing chain can be divided into three main modules: the first module is a source coding system, which is responsible for inputting audio and data source files, and encoding source code for different source files according to relevant standards, and then encoding The data stream is multiplexed into a specific frame structure; the second module performs time domain interleaving, channel coding, etc. on the source coded frame data, and then converts the processed data into a bit stream; the last module For the signal modulation system, this part of the system will perform a series of processing such as quadrature phase shift keying modulation, frequency domain interleaving, differential modulation, orthogonal frequency division multiplexing on the input bit stream, and finally output the complete DAB baseband signal. Figure 1 shows the block diagram of the DAB signal modulation system.

Figure 1 DAB signal modulation system block diagram

2 DAB signal modulation system algorithm modeling

Figure 2 DAB signal modulation system block diagram

In order to finally realize the DAB baseband architecture signal modulation system in the FPGA chip, the algorithm layer is firstly modeled in the whole system. The block diagram of the DAB signal modulation system is shown in Figure 2. The algorithm layer model of the DAB signal modulation system has the following main modules: a trigger sequence detection subsystem, a system clock generation subsystem, a coded QPSK mapping system, a frequency interleaving subsystem, a differential modulation subsystem, an OFDM subsystem, and the like. It should be noted that almost every subsystem (such as frequency interleaving system) has its own clock domain, and the output provided by the system clock is much more complicated than a single clock signal.

2.1 Trigger Sequence Detection and System Clock Subsystem

In the DAB signal modulation system, a corresponding sequence detection system needs to be designed to identify the received data stream. When the data stream does not contain the trigger sequence, the DAB signal modulation system is in a dormant state, and the system output is zero; when detected When the sequence is triggered, the sequence detection system will issue an enable signal to cause the DAB signal modulation system to process the data stream following the trigger sequence.

The state machine is an intuitive and efficient way to implement this trigger sequence identification subsystem. Since the DAB signal modulation system to be designed is a complex real-time signal processing system, it is necessary to establish a global clock for the system to regulate the processing timing. It should also be noted that the processing timing between the various subsystems of the system must be coordinated. Otherwise, the DAB baseband signal at the output end will be destroyed by the physical layer or the logical layer frame structure. The global clock provides a coordination function for each subsystem. The overall timing framework. At the same time, subsystems that require complex processing (such as frequency interleaving subsystems, differential modulation subsystems, etc.) can build their own clock domains and process control signals in a global clock architecture. The establishment of the global clock system mainly relies on the combination of the counter and the logic comparison module.

2.2 Coded QPSK Mapping Subsystem

Assuming that the bit code stream received by the DAB signal modulation system already contains the information of the block partition structure, the QPSK symbol mapping subsystem will restore the symbol pair including the block division from the received encoded data stream, and the code is The stream performs QPSK modulation, which maps the restored symbol pairs to QPSK symbols. The algorithm of this subsystem is relatively intuitive. In the processing of restoring symbol pairs, the serial-to-parallel conversion involved is realized by the solution time division multiplexing algorithm, and the mapping of QPSK symbols is realized by the lookup table.

2.3 Frequency Interleaving Subsystem

The frequency interleaving algorithm will change the corresponding order between the QPSK symbols and the carrier. Real-time processing requirements greatly increase the complexity of the algorithm model of the frequency interleaving subsystem. In order to realize the real-time frequency interleaving processing of the input QPSK symbol stream, this paper designs a double buffer space algorithm model, as shown in Figure 3.

Figure 3 Double buffer space algorithm model

The core idea of ​​the double buffer space algorithm model is to provide two parallel buffer spaces. In the same OFDM symbol period (384 QPSK symbol periods), one buffer space receives the QPSK code stream, and the other buffer space is in the read lock state, and performs static frequency interleaving processing. At this point the input of the system is connected to the previous buffer space, and the output of the system is provided by the second buffer space. After the end of one OFDM symbol period, the working states of the two buffer spaces are reversed, and the buffer space for receiving the QPSK code stream is in the read-lock state, performing static frequency interleaving processing and providing system output; and the buffer space of the previous frequency interleaving is It is in the read-in state and receives a serial QPSK code stream from the input of the system.

2.4 Differential Modulation Subsystem

After the frequency interleaving subsystem processes, the QPSK-modulated symbol stream changes its carrier correspondence in one OFDM symbol period, so that the information flow in the frequency domain is disordered to a certain extent, and the signal resistance is improved. The ability to decline. However, since the modulation mode is QPSK, the information is modulated on the absolute phase of the carrier, which requires high stability of the reference reference phase at the receiving end. Otherwise, the error of the code information may occur due to the instability of the reference reference phase. Translation situation. In order to further enhance the reliability of the system, differential modulation is introduced in the DAB baseband signal processing process, and the QPSK symbol stream is converted into a DQPSK symbol stream, thereby modulating the information on the relative phase information of the carrier, thereby improving the stability of the system.

In the differential modulation system algorithm model, a local storage area is required to store the frequency reference symbols, and the differential modulation processing flow of each frame signal is as follows. When the frame header is empty, the system does not do any processing and directly outputs an empty signal. During the frequency reference symbol period, the input of the system is still a null signal, but the local memory area will provide the frequency reference symbol at the output of the system and introduce the frequency reference symbol into the feedback buffer. When the first FIC symbol is input, the frequency reference symbol of the feedback buffer will be synchronized with it, the corresponding QPSK symbols are added by modulo 8, the corresponding subcarriers are differentially modulated, and the output terminals are added by modulo 8. The coded DQPSK symbol is introduced into the feedback buffer. When the second FIC symbol is input, the modulo 8 is added based on the differentially modulated previous OFDM symbol in the feedback buffer. When all the OFDM symbols of a frame signal are processed, the feedback buffer is cleared. Zero, in preparation for reloading the phase reference symbol. Figure 4 depicts the algorithmic model of a differential modulation system.

Figure 4 Differential modulation system algorithm model

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