Nand-Flash/eMMC (Nand-Flash with Flash Controller) as a non-linear macrocell mode memory provides a cost-effective solution for solid-state mass storage implementation. Nand-Flash memory has the advantages of large capacity and fast rewriting speed, and is suitable for storage of large amounts of data. Therefore, it is more and more widely used in various fields such as embedded products, smart phones, and cloud storage databases.
Figure 1 Nand-Flash and eMMC chip
Memory device lifetime
The motherboard that uses Nand-Flash has a data loss program, which is an accident that has made countless engineers creepy. Seeing that the program disappeared with the use of the program, can only be anxious and unable to start. An experienced engineer takes a knife and falls into a new material, and the code is continued for half a project cycle. Going back and nowhere to vent is also a big change for manufacturers and brands. Although it is still affordable to change a few pieces of Nand-Flash, after all, this is a bottomless pit. It is better to go deeper into the cause of the problem, otherwise it will not be able to make up for the deficit.
In the device data sheet, the block erasing life of Nand-Flash is usually 100,000 times, and the block erase of EMMC is up to 10,000 times. Similarly, EEPROM, SD card, CF card, U disk, Flash hard disk, etc. There is a problem with the write life of the media. When the file system writes data to the underlying memory block of the write data, the data in the block is read out first, and after the erase block is cleaned, the data to be written is written back to the memory together with the previously read block data. Inside, if the file system write balance is not handled well, especially if it is required to record data such as frequent write block operations within 1 minute, it is possible to write the Nand-Flash or EMMC blocks badly.
Storage device loses data and loses data
When the file system writes data to the memory, it is conventional to first read out the data in the block. After the erase block is clean, the data to be written is written back to the memory together with the previously read block data. If the device unexpectedly loses power or even voltage instability during the erase block process or during the write back data, it will cause data loss or damage. If the missing data is a file system's FAT table, it will cause the file system to crash. This is why the system program is unable to initiate catastrophic consequences.
System data protection scheme
In many cases, the product is burned and tested repeatedly before leaving the factory. No matter how toss, there will be no loss of the program. The possible factor is that the test equipment guarantees a stable running power output, so the normal Flash protection mechanism in the system is reliable.
Relative to the actual use of the user, in order to avoid the damage of Flash, it is necessary to strictly follow the product description, especially to avoid artificially powering down during the flash erase or write process. This is a big tab for the use of memory devices. Even for a good device, such non-standard use will greatly shorten its life. Moreover, the power supply system in different environments has various kinds of programs. When the power supply does not meet the power requirement, the program has a low detection threshold for the low power of the power supply. At this time, forcibly starting the system or performing the write operation will further increase the system power consumption fluctuation, and the huge ripple is also Will cause the CPU to misuse the storage.
To solve this problem for the software side:
When debugging the system or in the field, it is recommended to use software reset to avoid the manual reset operation by power failure; if there is power failure, add the printing information such as "system loading completed", "data saving completed" and other instructions. ;
The software adopts the Flash equalization saving algorithm to efficiently adjust the size of the Flash area erased when the data is changed;
The data can be written into the memory or the ferroelectric memory first, and then the data can be moved to the large memory periodically, thereby reducing the number of Nand-Flash and EMMC erasing;
In the program to add or improve the threshold of power supply detection, the program ensures that all chips under the power system can work normally at this threshold.
During the reading and writing process, the bad block table is carefully maintained and updated to avoid the program writing bad blocks. Check the ECC when reading data to ensure that the data is correct.
Consider from a hardware perspective:
Usage avoids sudden power loss during flash erase or write process;
Design and manage the power supply system of the control core to prevent the ripple of the power supply system due to transient changes during startup and operation;
With the power-down detection circuit, when the external power supply is detected, the file system is quickly shut down and the operation of writing data to the file system is stopped.
Add the file system power domain UPS power supply, and even the whole machine power-down battery life;
For users who use small-capacity storage such as EEPROM, it is conceivable to replace it with a ferroelectric non-volatile memory FRAM made of a highly reliable ferroelectric material. FRAM can be read and written as fast as RAM. The data can be stored for 10 years after power down, and its read/write life is up to 10 billion times. It is more reliable than EEPROM and other non-volatile memory systems, with simpler structure and lower power consumption.
Figure 2 Ferroelectric material non-volatile memory
The following is a brief introduction to the design of a UPS circuit based on a Farad capacitor. The main points are as follows:
Due to the individual differences in capacitance, the rate at which the capacitor stores charge is different. There is a problem that the voltage exceeds the withstand voltage due to overcharge. When there are multiple farad capacitors in the circuit, it needs to be equalized;
In order to ensure that the capacitor can be fully charged, the source terminal needs to be charged by a constant current source;
In order to maintain the capacitor voltage stability and reduce the power consumption of the charging circuit, an overvoltage detection circuit needs to be added;
If the power supply system with a voltage higher than the upper limit of the voltage of the farad capacitor provides power-off, the Vcc_backu terminal must be implemented after the BOOST boost circuit, and the EN pin is turned off when the system is normal (during charging).
Figure 3 UPS core circuit based on farad capacitor
When the system power is normal, the charging circuit charges the UPS. When the system power is lost, the UPS discharge provides backup power to the system. It is recommended that the UPS can continue to supply the file system with a power supply of no less than 10 seconds after the power is turned off. During the 10 second battery life, the system can report the abnormal power status and keep it in time. Temporary important data, close the file system, ensure system stability, avoid damage to the file system in the event of power loss, affecting the normal startup of the application.
Figure 4 suggests UPS charge and discharge timing
In addition, the power-down condition of the system needs to be realized by the power-down detection circuit. Use a comparator device, pay attention to the power supply using the Output_VCC terminal to ensure that the comparator can still work when the external power is lost. The comparator negative terminal is connected to a reference voltage, and the reference voltage is supplied by a Zener diode. During normal power supply, the comparator output voltage is determined by the feedback terminal's voltage divider; when the power is off, the comparator outputs a low level. At this time, the processor is still not powered down, and the status information can be processed in time. Another power-down detection is available for other functions.
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