In high-speed real-time or non-real-time signal processing systems, the use of large-capacity memory for data caching is an indispensable link, and one of the key and difficult points in system implementation. SDRAM (Synchronous Dynamic Random Access Memory) has the advantages of low price, high density, and fast data read and write speed, thus becoming the preferred storage media sanction for data caching. However, the SDRAM memory structure is quite different from the RAM, and its control timing and mechanism are also complicated, which limits the use of SDRAM. At present, although some parents can provide transparent interfaces with SDRAM, their scalability and flexibility are not enough to meet the requirements of real systems and limit the use of SDRAM.
Under the premise of reading the SDRAM data file in detail, referring to ALTERA's IP core, a general-purpose SDRAM controller is designed by using programmable devices (CPLD, FPGA). It is highly flexible and can be easily combined with other data acquisition and analysis systems, as shown in Figure 1. In this system, the SDRAM storage array caches high-speed data from the intermediate frequency. After the memory is full, the data is slowly read out to the data processing module. The design of the SDRAM control module will be described in detail below.
1 SDRAM memory bank structure
The SDRAM memory module is composed of an SDRAM memory chip, and the number of memory chips on the memory module is determined according to the capacity of the memory module. Taking the TIM16LSDT6464A SDRAM memory module manufactured by MICRON as an example, the structure of SDRAM is briefly introduced.
The MIT16LSDT6464A has a memory capacity of 512M Byte and consists of 16 memory chips MT46LC32M8A2 with a capacity of 32M Byte. The 16-chip memory chips are divided into two levels, each of which has a data bit width of 8 bits. 8 slices and a 64-bit data width. The data lines and controls of each memory chip are multiplexed. The read and write operations on the memory stick are based on the memory chipset, and the group number is determined by the chip select signals S0, S1, S2, and S3 of the memory stick. S0, S2 control chipset 1, S1, S3 control chipset 2.
The main signals of the SDRAM memory chip are control signals, control signals, and data signals, all of which are synchronous input and output signals of the working clock.
The control signals mainly include: CS (chip select signal), CKE (clock enable signal), DQM (input and output enable signals), CAS, RAS, WE (read and write control command words). Various control commands can be generated through various logical combinations of CAS, RAS, and WE.
The address signals are: BA0 and BA1 page address selection signals, A0~A12 address signals, row and column address selection signals. It is determined by time division multiplexing whether the address is a row address or a column address. In the read and write operations, the page address, the row address, and the column address are sequentially given on the ground line, and the memory cell address is finally determined.
The data signals are: DQ0~DQ7, bidirectional data. It is enabled to be controlled by DQM.
The operating mode of the SDRAM is selected by setting the operating mode register by the LOAD MODE REGISTER command. The setting parameters are Reserved Burst Mode (WB, Write Burst Mode), Operation Mode (Op Mode), CAS Latency (CAS Delay), Burst Type (BT, Burst Type), Burst Length. (burst length).
2 SDRAM basic read and write operations
The basic read operation of the SDRAM requires the control line and the address line to issue a series of commands to complete. The BANK activation command (ACTIVE) is issued first, and the corresponding BANK address (given by BA0, BA1) and the row address (given by A0~A12) are latched. After the BANK activates the command, it must wait for more than tRCD (SDRAM's RAS to CAS delay indicator) time to issue a read command word. After the CL (CAS delay value) operating clocks, the read data appears in sequence on the data bus. At the end of the read operation, a precharge (PRECHARGE) command is issued to the SDRAM to close the page that has been activated. Wait for the tRP time (PRECHARGE) command to close the page that has already been activated. After waiting for the tRP time (after the PRECHAREG command, the tRP time can be accessed again), you can start the next read and write operation. The SDRAM read operation is only Burst Mode, and the burst length is 1, 2, 4, and 8 optional.
The basic write operation of the SDRAM also requires the control line and the address line to issue a series of commands to complete. The BANK activation command (ACTIVE) is issued first, and the corresponding BANK address (given by BA0, BA1) and the row address (given by A0~A12) are latched. After the BANK activates the command, it must wait for a time greater than tRCD to issue a write command word. The write command can be written immediately, and the data to be written is sequentially sent to the DQ (data line). The tWR time is delayed after the last data is written. Issue a precharge command to close the page that has been activated. After waiting for the tRP time, you can expand the next operation. Write operations can be either burst write or non-burst write. The burst length is the same as the read operation.
The specific requirements of tRCD, tRP, and tWR are detailed in the data sheet provided by the SDRAM manufacturer. The number of working clocks to wait is determined by the combination of the minimum values ​​of tRCD, tRP, and tWR, and the operating clock period.
It can be concluded from the above that the read and write operations of SDRAM are composed of a series of commands, so the read and write operations have clock loss, and the working clock rate is not equal to the read and write rates that SDRAM can achieve. However, since the SDRAM has a burst read and write mode, that is, a series of consecutive addresses of data can be read and written, thereby improving efficiency. When the burst length is the entire page, the read and write speeds are the fastest. The calculation formula for random read and write speeds is:
Furite/read=working clock frequency (HzHzHhdkkdk ss dkkdkdkd,,,m,mddddd)×data width (bytes)×burst read/write length/number of clocks required for operation
To increase storage density, SDRAM uses silicon capacitors to store information. There is always leakage current flowing through the capacitor, so in order not to lose information, the capacitor must be refreshed periodically. The external control logic must periodically issue a refresh command to the memory module as required to ensure that each unit is refreshed within the specified time.
3 initialization operation
SDRAM must be initialized after power-on, as follows:
(1) The system should wait for 100~200μs after power-on. At least one empty operation or instruction prohibit operation after the waiting time has elapsed.
(2) Perform the PRECHARGE command on all chips to complete the precharge.
(3) Two AUTO REFRESH commands are issued to each group of memory chips, so that the refresh counter inside the SDRAM chip can enter the normal running state.
(4) Execute the LOAD MODE REGISTER command to complete the setting of the SDRAM working mode.
After completing the above steps, the SDRAM enters the normal working state and waits for the controller to read, write, and refresh it.
4 SDRAM controller design
4.1 Functional Description
In a system with SDRAM as a cache, it is very flexible to use a programmable device to control it. In order to make the design modular and reusable, a simplified SDRAM interface circuit is designed. This masks the complexity of the SDRAM operation, while other logic modules can access the SDRAM through the interface circuit. In addition, since the entire SDRAM controller is written in the VHDL language, it can be adapted to different requirements as long as it is simply modified, and has great flexibility.
Referring to FIG. 2, the main function performed by the SDRAM controller is to parse the command word of the CMD[2:0] and the address of the ADDR terminal to generate the corresponding control timing of the SDRAM.
CLK is the input working clock port.
ADDR is the input address port. The controller parses it into the corresponding chip select, page, and row and column addresses. Take a MIT16LSDT6464A memory module as an example, the size is 512Mbyte (2 29 byte). The data bit width is 64 bits (8 bytes), and the address line ADDR should be 26. The address can be mapped as follows: ADDR[25] corresponds to the memory chipset number; ADDR[24:23] corresponds to the page number; ADDR[22:10] corresponds to the row number; ADDR[9:0] corresponds to the column number.
DATAIN is the write data port, 64 bits wide.
DATAOUT is the read data port, 64 bits wide.
RD_OE is the read data enable port. When it is 1, it means that data will appear on the DATAOUT port in sequence from the next clock.
WR_OE is the write data enable port. When it is 1, the write data should appear on the DATAIN port in turn.
CMD[2:0] is the command input port, which means read and write memory wait operations. Among them, CMD=“000†means no operation, the memory stick is handed over to the controller for management, and the refresh operation is completed; the REFRESH command specifies the special refreshed memory chip signal by the external logic, the group number is given by the low bit of ADDR; the LOAD_MODE command is executed. The memory bar working register is initialized. The initialization value is determined by the lower 13 bits of DATAIN. The memory chipset number is also given by the low bit of ADDR. Similarly, the low bit of ADDR also determines the memory chipset number corresponding to the precharge operation.
CMDACK is the command response port, indicating that the command has been executed, allowing the external logic to issue the next action to the controller.
4.2 state machine
Figure 3 is a state transition diagram of the SDRAM controller. Each state in the state diagram contains a series of substate transitions (sequential commands are issued to the SDRAM memory bank), and each substate completes a functional operation. The initialization operation includes the entire process of memory module initialization described above, and the default value of the working register is specified in the VHDL program. The operating mode of the memory module can be changed later by the LOAD_MODE command. After the initialization is completed, the memory stick enters the Idel state, the refresh counter starts to work, and the controller starts responding to the external logic operation request.
The refresh counter operation is a separate process. The initial value of the refresh counter is determined by the memory chip requirement, the number of memory modules, and the controller operating frequency. For example, in this design, the MT48LC32M8A2 memory chip used needs to refresh at least 8196 times in summer within 64ms. The MIT16LSDT6464A type memory module has two sets of memory chips, that is, it is required to issue 8196×2 self-refresh (AUTO REFRESH) instructions within 64ms. The system operating clock is 46.66MHz, so when controlling a single MIT16LSDT6464A, the initial value of the refresh counter is at most (64ms/8196/2)×6, 46.66MHz, that is, 182. After starting the work, whenever the refresh counter value is reduced to 0, A refresh command is issued to the memory chipset in turn to ensure that the data in the SDRAM is not lost. A refresh request is a memory request; read and write operations are external requests. There is request arbitration logic in the Idel state. When internal and external requests occur simultaneously, the internal request is preferentially guaranteed and the state is transferred to the refresh operation. When the refresh operation ends, it returns to the Idel state and starts responding to the external request. In response to an external request, a positive pulse occurs in the acknowledge signal CMDBAK. It notifies the external logic that the request has been responded and the request can be revoked. In the refresh operation state, there are also a number of timers whose size is equal to the memory chip signal managed by the controller. Record and judge the group number of the memory chip corresponding to the refresh operation, and generate a corresponding chip select signal.
After responding to read and write requests, the state transitions from Idel to read and write states. At the same time, the read and write addresses and the written data are latched to the controller. The controller parses out the CS signal, page address, row address, and column address from the read/write address. A series of commands (ACTIVE, READ/WRITE with AUTO PRECHARGE) are issued to the memory module to complete the read and write operations. For the sake of simplicity, the controller issues read and write commands to the SDRAM with AUTO PRECHARGE, and then the internal logic of the SDRAM. The PRECHARGE instruction is automatically issued at the end of the read and write process (when the READ/WRITE instruction is issued, the address line A10 is assigned a value of 1, the AUTO PRECHARGE function is turned on). 4 and 5 are timing charts for performing read and write operations by using the controller, respectively. The CAS latency for read operations is two clocks.
The SDRAM controller has been applied in an IF data mass storage system. The data receiving logic sorts the received intermediate frequency sampling data (spliced ​​into 64 bits) and stores it in the SDRAM array through the SDRAM controller. After being filled, the data output logic takes the intermediate frequency data out of the memory stick through the SDRAM controller and transmits it to the upper computer. Its VHDL code passes the Quartus II simulation, synthesis, layout, and routing in ATERA's FPGA-EP1C6Q240. It takes up 499 logic cellk and consumes 8% of logical resources. There are plenty of resources available for other logical units.
The basic working principle of SDRAM and the implementation of a simple general-purpose SDRAM controller are introduced above. The control mechanism of SDRAM is more complicated, with multiple burst read and write modes and working modes (refer to the SDRAM data sheet for details). However, depending on the implementation application, a subset of them (basic read, write, refresh operations) can be implemented to meet the needs of the actual system. The use of SDRAM to achieve high-capacity high-speed data buffer has obvious advantages. The use of programmable devices to implement SDRAM controllers makes it more flexible, and its application prospects are broad.
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